The present disclosure relates generally to integrated circuit (IC) design, and more particularly, to a method for protecting the core circuitry of an integrated circuit (IC) from damage that may be caused by electrostatic discharge (ESD).
A gate oxide of any metal-oxide-semiconductor (MOS) transistor, in an integrated circuit, is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than supply voltage. It is understood that a regular supply voltage is 5.0, 3.3, 3.1 volts, or lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current, are extremely small. So, it is of critical importance to discharge any static electric charge, as it builds up, before it accumulates to a damaging voltage.
ESD is only a concern to an integrated circuit before it is installed into larger circuit assemblies, such as a printed circuit board (PCB), and before the PCB is connected to an operating power. This susceptible period includes production, storage, transport, handling, and installation. After the power is supplied, the power supplies and the structures can easily absorb or dissipate electrostatic charges.
ESD protection module is typically added to ICs at the bond pads. The pads are the connections to the IC, to or from outside circuitry, for all electric power supplies, electric grounds, and electronic signals. Such added circuitry must allow normal operation of the IC. That means that the protection module is effectively isolated from the normally operating core circuitry because it blocks current flow through itself, to ground, or any other circuit, or pad. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to some pads, and electronic signals generated by the core circuitry of the IC are supplied to other pads for delivery to external circuits and devices. In an isolated, unconnected IC, all pads are considered to be electrically floating, or of indeterminant voltage. In most cases, that means that the pads are at ground, or zero voltage.
ESD can arrive at any pad. This can happen, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day, and then touches a grounded metal object. In an isolated IC, ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when ESD acts as a power supply, at a randomly selected pad, the protection module acts differently than it does when the IC is operating normally. When an ESD event occurs, the protection module must quickly become current conductive, so that the electrostatic charge is conducted to VSS ground and thus, dissipated before damaging voltage builds up.
ESD protection module, therefore, has two states. In a normally operating IC, ESD protection module appears invisible to the IC by blocking current through itself and thus, having no effect on the IC. In an isolated, unconnected IC, ESD protection module serves its purpose of protecting the IC by conducting an electrostatic charge quickly to VSS ground before a damaging voltage can build up.
Salicide is used widely in deep submicron CMOS technology in lowering the sheet resistance of poly resistors and the source or drain regions. In a typical ESD protection module design, a pad is connectable to an NMOS transistor which may also be connected, in parallel, with a parasitic BJT device. Each such circuit is referred to as a “finger” and many such fingers can be connected, in parallel, to dissipate the ESD current. However, full salicide CMOS technology, without using a “salicide-blocked” process, that includes salicide blocking and salicide removing steps, in an NMOS source/drain region, seriously jeopardize the performance of the ESD protection module. The non-uniform turn-on behaviors between ESD protection modules, or fingers, and the filament and thermal runaway, at the MOS channel, of the NMOS transistor, are the causes for such poor ESD performance. Since adding a ballast resistor between the pad and the drain of the NMOS transistor can help the BJTs, in different fingers, to turn on uniformly, removing the salicide on the drain of the NMOS transistor can create such a ballast resistor, thus, helping the uniform turn-on of the parasitic BJTs in different fingers.
Another previous proposed method called multi-finger turn-on (MFT) technique has to insert salicide poly resistors between the source region of the NMOS transistor and the ground to make sure all the fingers will be triggered in the ESD event. However, inserting a resistor like that may cause other issues. For example, the sheet resistance of the salicide poly resistor may be deviated after an ESD event has happened, thereby, deviating the drivers' I-V curve after ESD stressing.
As the technology advances, high voltage tolerant ESD design is often adopted on various high voltage tolerant (HVT) applications. What is increasingly in need is an improved ESD protection module.